The present invention relates generally to the implementation of a relaxed ordering attribute in PCI-X systems. Particularly, the present invention facilitates bypassing of the transaction order queue by read completion transactions when a relaxed ordering attribute is set accordingly.
This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art,
A conventional computer system typically includes one or more central processing units (CPUs) and one or more memory subsystems. Computer systems also typically include peripheral devices for inputting and outputting data. Some common peripheral devices include, for example, monitors, keyboards, printers, modems, hard disk drives, floppy disk drives, and network controllers. The various components of computer system communicate and transfer data using various buses and other communication channels that interconnect the respective communicating components.
One of the important factors in the performance of a computer system is the speed at which the CPU operates. Generally, the faster the CPU operates, the faster the computer system can complete a designated task. One method of increasing the speed of a computer is using multiple CPUs, commonly known as multiprocessing. With multiple CPUs, tasks may be executed substantially in parallel as opposed to sequentially.
However, the addition of a faster CPU or additional CPUs can result in different increases in performance among different computer systems. Although it is the CPU that executes the algorithms required for performing a designated task, in many cases it is the peripherals that are responsible for providing data to the CPU and storing or outputting the processed data from the CPU. When a CPU attempts to read or write to a peripheral, the CPU often xe2x80x9csets asidexe2x80x9d the algorithm that is currently executing and diverts to executing the read/write transaction (also referred to as an input/output transaction or an I/O transaction) for the peripheral. As can be appreciated by those skilled in the art, the length of time that the CPU is diverted is typically dependent on the efficiency of the I/O transaction.
Although a faster CPU may accelerate the execution of an algorithm, a slow or inefficient I/O transaction process associated therewith can create a bottleneck in the overall performance of the computer system. As the CPU becomes faster, the amount of time it expends executing algorithms becomes less of a limiting factor compared to the time expended in performing an I/O transaction. Accordingly, the improvement in the performance of the computer system that could theoretically result from the use of a faster CPU or the addition of additional CPUs may become substantially curtailed by the bottleneck created by the I/O transactions. Moreover, it can be readily appreciated that any performance degradation due to such I/O bottlenecks in a single computer system may have a stifling affect on the overall performance of a computer network in which the computer system is disposed.
As CPUs have increased in speed, the logic controlling I/O transactions has evolved to accommodate I/O transactions. Such logic, usually referred to as a xe2x80x9cbridge,xe2x80x9d is typically an application specific integrated circuit (ASIC). Thus, most I/O transactions within a computer system are now largely controlled by these ASICs. For example, Peripheral Component Interconnect (PCI) logic is instilled within buses and bridges to govern I/O transactions between peripheral devices and the CPU.
Today, PCI logic has evolved into the Peripheral Component Interconnect Extended (PCI-X) to form the architectural backbone of the computer system. PCI-X logic has features that improve upon the efficiency of communication between peripheral devices and the CPU. For instance, PCI-X technology increases bus capacity to more than eight times the conventional PCI bus bandwidth. For example, a 133 MB/s system with a 60 bit PCI bus running at 33 MHz is increased to a 1060 MB/s system with the 64 bit PCI bus running at 133 MHz.
An important feature of the new PCI-X logic is that it can provide backward compatibility with PCI enabled devices at both the adapter and system levels For example, although PCI devices cannot run in PCI-X mode, the bus is still operable in PCI mode. However, the devices will operate at the slower PCI speed and operate according to PCI specifications. Thus, PCI-X devices will operate according to PCI-X specifications, while PCI devices will operate according to PCI specifications without having an adverse affect on the PCI-X devices, if the PCI and PCI-X devices are located on separate buses.
PCI-X logic devices enable a requesting device to make only one data transaction and relinquish the bus, rather than reissuing the transaction on the bus to poll for a response. PCI-X parameters also enable the requesting device to specify in advance the specific number of bytes requested, thus eliminating the inefficiency of prefetches. Additionally, PCI-X bus logic permits a requestor to specify the ordering of the transactions. Previously, ordering requirements were not specific to read completion transactions in PCI enabled devices. Although, PCI logic also governs general ordering rules, such as memory writes being retrieved and delivered to the requestor first, PCI enabled devices do not accommodate for the bypass of memory write transactions by read completion transactions. However, PCI-X specifications facilitate read completion transactions in bypassing the transaction order queues, even if there are memory write transactions outstanding.
Any device that requires a significant number of memory write transactions from the central processing unit potentially introduces performance degradations on other devices. There is a need for a technique for read completion transactions to bypass memory write transactions without disrupting the ordering rules maintained within the bridges. Thus, the relaxed ordering feature of the PCI-X logic results in significantly higher system performance, because relaxed ordering facilitate the bypass of memory write transactions by read completions.
The present invention may address one or more of the problems discussed above.
Certain aspects commensurate in scope with the originally claimed invention are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In accordance with one aspect of the present invention, there is provided a method for bypassing a transaction order queue for PCI-X transactions. The present technique involves determining whether the transaction is subject to a relaxed ordering attribute. If the transaction is subject to relaxed ordering, then the present technique facilitates completion of the transaction by bypassing the transaction order queue. Thus, the present method enables a read completion transaction to bypass the transaction order queue if a relaxed ordering attribute is set accordingly.